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Semiconductor
February 1999
CT T ODU MEN E PR PLACE -7747 ET OL RE -442 OBS ENDED -800 M ns 1 rris.com M io licat ECO ha NO R ntral App entapp@ c e C : Call or email
CD22354A, CD22357A
CMOS Single-Chip, Full-Feature PCM CODEC
TO SLIC
[ /Title (CD22 354A, CD223 57A) /Subject (CMO S SingleChip, FullFeature PCM CODE C) / Author () /Keywords (Harris Semiconductor, RSLIC 18, Telecom, SLICs, SLACs , Telephone, Telephony, WLL, Wireless Local Loop,
Features
* Meets or Exceeds All AT&T D3/D4 Specifications and CCITT Recommendations * Complete CODEC and Filtering Systems: No External Components for Sample-and-Hold and Auto-Zero Functions. Receive Output Filter with (SIN X)/X Correction and Additional 8kHz Suppression * Variable Data Clocks - From 64kHz . . . . . . . . . . . . . . . . . . . . . 2.1MHz * Receiver Includes Power-Up Click Filter * TTL or CMOS-Compatible Logic * ESD Protection on All Inputs and Outputs
Description
The CD22354A and CD22357A are monolithic silicongate, double-poly CMOS integrated circuits containing the band-limiting filters and the companding A/D and D/A conversion circuits that conform to the AT&T D3/D4 specifications and CCITT recommendations. The CD22354A provides the AT&T -law and the CD22357A provides the CCITT A-law companding characteristic. The primary applications for the CD22354A and CD22357A are in telephone systems. These circuits perform the analog and digital conversions between the subscriber loop and the PCM highway in a digital switching system. The functional block diagram is shown below. With flexible features, including synchronous and asynchronous operations and variable data rates, the CD22354A and CD22357A are ideally suited for PABX, central office switching system, digital telephones as well as other applications that require accurate A/D and D/A conversions and minimal conversion time.
Applications
* PABX * Central Office Switching Systems * Accurate A/D and D/A Conversions * Digital Telephones * Cellular Telephone Switching Systems * Voice Scramblers - Descramblers * T1 Conference Bridges * Voice Storage and Retrieval Systems * Sound Based Security Systems * Computerized Voice Analysis * Mobile Radio Telephone Systems * Microwave Telephone Networks * Fiber-Optic Telephone Networks
Ordering Information
PART NUMBER CD22354AE CD22357AE TEMP. RANGE (oC) PACKAGE PKG. NO. -40 to 80 -40 to 80 16 Ld PDIP E16.3 16 Ld PDIP E16.3
Pinout
CD22354A, CD22357A (PDIP) TOP VIEW
V- 1 GND 2 VFRO 3 V+ 4 FSR 5 DR 6 BCLKR/ 7 CLKSEL MCLKR/ 8 PDN 16 VFX1+ 15 VFX114 GSX 13 TSX 12 FSX 11 DX 10 BCLKX 9 MCLKX
Functional Block Diagram
FULL-FEATURE PCM CODEC
FROM SLIC GSX VFX1VFX1+ 14 15 16 + ANTI-ALLAS FILTER XMIT LOW PASS FILTER XMIT HIGH PASS FILTER TRANSMIT COMPARATOR D/A LADDER
SIGN BIT INT. PARALLEL TO SERIAL 11 10 12 13 9 8 5 D/A REGISTER SERIAL TO PARALLEL RCV DIGITAL +5V -5V 4 1 V+ V7 6 DX BCLKX FSX TSX MCLKX DDIGITAL IN MCLKR/ PDN FSR BCLKR/ CLKSEL DR DDIGITAL OUT XMIT VREF S.A.R. XMIT CLOCK CIRCUIT RCV CLOCK CIRCUIT GND 2 RCV VREF XMIT DIGITAL
BAND GAP REFERENCE
VFRO
3
SMOOTHING FILTER
RECEIVE LOW PASS FILTER
RECEIVE D/A LADDER
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1999
File Number
1682.4
4-165
CD22354A, CD22357A
Absolute Maximum Ratings
DC Supply-Voltage, (V+) . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to 7V DC Supply-Voltage, (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to -7V DC Input Diode Current, IIK (VI < V- -0.5V or VI > V+ 0.5V) . . . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK (VI < V- -0.5V or VO > V+ 0.5V). . . . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, Per Output IO (V- -0.5V < VO < V+ 0.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC Supply/Ground Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mA Power Dissipation Per Package (PD): For TA = -40oC to 60oC . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW For TA = 60oC to 85oC . . . . . . . . . . . . Derate Linearly at 8mW/oC to 300mW
Thermal Information
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Operating-Temperature Range (TA) . . . . . . . . . . . . . . -40oC to 80oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER STATIC SPECIFICATIONS Positive Power Supply Negative Power Supply Power Dissipation (Operating) Power Dissipation (Standby)
At TA = 25oC SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
V+ VPOPR PSTBY V+ = 5V V- = -5V
4.75 -4.75 -
5 -5 75 9
5.25 -5.25 90 15
V V mW mW
Electrical Specifications
PARAMETER STATIC SPECIFICATIONS Analog Input Resistance Input Capacitance Input Leakage Current, Digital Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Open State Output Current Input Leakage Current, Analog
At TA = 0oC to 70oC; V+ = 5V 5%, V- = -5V 5% SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
RINA CIN II VIL VIH VOL VOH IOZ II All Logic and Analog Inputs VI = 0V or V+ IIL = 10A (Max) IIH = 10A (Max) IOL = 3.2mA IOH = 1.0mA GND < DX < V+ -2.5V VFX < 2.5V
10 -10 2 2.4 -10 -200
5 -
10 0.8 0.4 10 200
M pF A V V V V A nA
4-166
CD22354A, CD22357A
Electrical Specifications
PARAMETER V+ = 5V 5%, V- = -5V 5%, BCLKR = BCLKX = MCLKX = 1.544MHz, VIN = 0dBm0, TA = 0oC to 70oC SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
TRANSMIT AND RECEIVE FILTER TRANSFER CHARACTERISTICS Transmit Gain (Relative to Gain at 1020Hz) Input Amplifier Set to Unity Gain GRX f = 16Hz f = 50Hz f = 60Hz f = 200Hz f = 300Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz f 4600Hz, Measure 0 - 4kHz Response Receive Gain (Relative to Gain at 1020Hz) (Includes (SIN X)/X Compensation) GRR f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz -1.8 -0.15 -0.35 -0.7 -40 -30 -26 -0.1 0.15 0.05 0 -14 -32 dB dB dB dB dB dB dB dB dB
-0.15 -0.35 -0.9 -
-
0.15 0.05 0 -14
dB dB dB dB
AC Specifications
Unless otherwise specified, the following conditions apply: V+ = 5V 5%, V- = -5V 5% GNDA, GNDD = 0V, FFX = 1020Hz at 0dBm0 Transmit input amplifier operating in a unity gain configuration Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Receive output is measured single-ended. All output levels are (SIN X)/X corrected.
Definition
AMPLITUDE RESPONSE Absolute Levels Definition: VREF = -2.5V Nominal 0dBm0 level. . . . . . . . . . . . . . . . . . . . . . 4dBm into 600 1.2276VRMS Maximum Overload Level: Voltage reference (VREF) of -2.5V . . . . . . . . . . . . . . . . 2.5V -Law 2.49V A-Law
AC Specifications Encoding Format at DX Output
CD22354A -LAW VIN (at GSX) = +Full-Scale VIN (at GSX) = 0V 1 1 0 VIN (at GSX) = -Full-Scale 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 CD22357A A-LAW (INCLUDES EVEN BIT INVERSION) 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0
4-167
CD22354A, CD22357A
Electrical Specifications
PARAMETER AC DISTORTION Signal to Total Distortion Xmit or RCV STDX, STDR Level = +3dBm0 Level = 0 to -30dBm0 Level = -40dBm0 Level = -55dBm0, XMT Level = -55dBm0, RCV Single Frequency Distortion Xmit or RCV Intermodulation (End-to-End Measurement) 2-Tone Transmit Delay, Absolute Transmit Envelope Delay Relative to tDAX SFDX, SFDR IMD VFX = -4dBm0 to -21dBm0 f1, f2 from 300 to 3400Hz 33 36 30 14 15 -46 dBc dBc dBc dBc dBc dBc SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
-
-
-41
dB
tDAX tDEX
f = 1600Hz f = 500-600Hz f = 600-1000Hz f = 1000-2600Hz f = 2600-2800Hz
-40 -40 -
280 170 70 40 90 180 -25 -25 60 110
315 220 145 75 105 200 90 125
s s s s s s s s s s
Receive Delay, Absolute Receive Envelope Delay Relative to tDAR
tDAR tDER
f = 1600Hz f = 500-600Hz f = 600-1000Hz f = 1000-2600Hz f = 2600-2800Hz
Electrical Specifications
PARAMETER AC GAIN TRACKING Transmit Gain Tracking Error GTX +3 to -40dBm0 -40 to -50dBm0 -50 to -55dBm0 Receive Gain Tracking Error GTR +3 to -40dBm0 -40 to -50dBm0 -50 to -55dBm0 Transmit Input Amplifier Gain, Open Loop AOL RL 1M at GSX 68 0.2 0.4 1.2 0.2 0.4 1.2 dB dB dB dB dB dB dB SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
4-168
CD22354A, CD22357A
Electrical Specifications
PARAMETER Transmit Input Amplifier Gain, Unity (Continued) SYMBOL ACL TEST CONDITIONS Unity Gain Configuration Inverting or Non-Inverting RL 10K, CL 50pF RL 10K, CL 50pF RL 600, CL 500pF MIN -0.01 TYP MAX 0.01 UNITS dB
Transmit Gain, Absolute Receive Gain, Absolute
GXA GRA
-0.15 -0.15
-
0.15 0.15
dB dB
Electrical Specifications
PARAMETER AC NOISE Transmit Noise NX VFXI- = GND VFXI+ = GND Receive Noise NR PCM Code Equivalent to 0V V+ Power Supply Rejection Transmit PSRR VFXI+ = 0V V+ = 5V + (100mVRMS) f = 0kHz to 50kHz VFXI- = 0V V- = -5V + (100mVRMS) f = 0kHz to 50kHz PCM Code = All 1 Code V+ = 5V + (100mVRMS) f = 0kHz to 4kHz f = 4kHz to 25kHz f = 25kHz to 50kHz V- Power Supply Rejection Receive PSRR PCM Code = All 1 Code V- = -5V + (100mVRMS) f = 0kHz to 4kHz f = 4kHz to 25kHz f = 25kHz to 50kHz Cross Talk Transmit to Receive Cross Talk Receive to Transmit CTXR CTRX VFXI- = 0dBm0 at 1020Hz DR = 0dBm0 at 1020Hz, VFXI- = 0V 40 12 -74 7 -83 15 -67 11 -79 dBrnc0 dBrn0p dBrnc0 dBrn0p dBc SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
V- Power Supply Rejection Transmit
PSRR
40
-
-
dBc
V+ Power Supply Rejection Receive
PSRR
40
-
-
dBc
37 36 40
-
-
dB dB dBc
40 36 -
-80 -76
-70 -70
dB dB dB dB
4-169
CD22354A, CD22357A
Electrical Specifications
PARAMETER AC TIMING Frequency of Master Clocks 1/tPM Depends on the Device Used and the BCLKR/CLKSEL Pin MCLKX and MCLKR Width of Master Clock High Width of Master Clock Low Rise Time of Master Clock Fall Time of Master Clock Set-up Time from BCLKX High (and FSX in Long Frame Sync Mode) to MCLKX Falling Edge Period of Bit Clock Width of Bit Clock High Width of Bit Clock Low Rise Time of Bit Clock Fall Time of Bit Clock Hold Time from Bit Clock Low to Frame Sync Hold Time from Bit Clock High to Frame Sync Set-up Time from Frame Sync to Bit Clock Low Delay Time from BCLKX High to Data Valid Delay Time to TSX Low Delay Time from BCLKX Low or FSX Low to Data Output Disabled Delay Time to Valid Data from FSX or BCLKX, Whichever Comes Later Set-up Time from DR Valid to BCLKR/X Low Hold Time from BCLKR/X Low to DR Invalid Set-up Time from FSX/R to BCLKX/R Low Hold Time from BCLKX/R Low to FSX/R Low tWMH tWML tRM tFM tSBFM MCLKX and MCLKR MCLKX and MCLKR MCLKX and MCLKR MCLKX and MCLKR First Bit Clock after the Leading Edge of FSX 160 160 100 1.536 1.544 2.048 50 50 MHz MHz MHz ns ns ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
tPB tWBH tWBL tRB tFB tHBF tHOLD tSFB tDBD tXDP tDZC tDZF CL = 0pF to 150pF VIH = 2.2V VIL = 0.6V tPB = 488ns tPB = 488ns Long Frame Only
485 160 160 0
488 -
15,725 50 50 -
ns ns ns ns ns ns
Short Frame Only
0
-
-
ns
Long Frame Only
80
-
-
ns
Load = 150pF plus 2 LSTTL Loads Load = 150pF plus 2 LSTTL Loads
0
-
180
ns
-
-
140
ns
50
-
165
ns
20
-
165
ns
tSDB tHBD tSF Short Frame Sync Pulse (1 or 2 Bit Clock Periods Long) (Note 1) Short Frame Sync Pulse (1 or 2 Bit Clock Periods Long) (Note 1)
50
-
-
ns
50
-
-
ns
50
-
-
ns
tHF
100
-
-
ns
4-170
CD22354A, CD22357A
Electrical Specifications
PARAMETER Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FSX or FSR) Minimum Width of the Frame Sync Pulse (Low Level) NOTE: 1. For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high. (Continued) SYMBOL tHBFI TEST CONDITIONS Long Frame Sync Pulse (from 3 to 8-Bit Clock Periods Long) MIN 100 TYP MAX UNITS ns
tWFL
64K Bit/s Operating Mode
160
-
-
ns
Pin Descriptions
PIN NO. 1 2 3 4 5 SYMBOL VGND VFRO V+ FSR DR BCLKR/CLKSEL Negative power supply, V- = -5V 5%. Analog and digital ground. All signals referenced to this pin. Analog output of RECEIVE FILTER. Positive power supply, V+ = 5V 5%. Receive Frame Sync Pulse which enables BCLKR to shift PCM data into DR. FSR is an 8kHz PULSE TRAIN. Receive Data Input. PCM data is shifted into DR following the FSR leading edge. The Receive Bit Clock, which shifts data into DR after the frame sync leading edge, may vary from 64kHz to 2.048MHz. Alternatively, the leading edge may be a logic input which selects either 1.536MHz/ 1.544MHz or 2.048MHz for Master Clock in synchronous mode and BCLKX is used for both transmit and receive directions. Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLKX, but best performance is realized from synchronous operation. When this pin is continuously connected low, MCLKX is selected for all internal timing. When this pin is continuously connected high, the device is powered down. Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLKR, but best performance is realized from synchronous operation. The Bit Clock which shifts out the PCM Data on DX. May vary from 64kHz to 2.048MHz, but must be synchronous with MCLKX. The THREE-STATE PCM Data Output which is enabled by FSX. Transmit Frame Sync Pulse input which enables BCLKX to shift out the data on DX. FSX is an 8kHz PULSE TRAIN. Open drain output which pulses low during the encoder time slot. Transmit gain adjust. Inverting input of the transmit input amplifier. Non-inverting input of the transmit input amplifier. DESCRIPTION
6 7
8
MCLKR/PDN
9
MCLKX BCLKX DX FSX TSX GSX VFXIVFXI+
10
11 12
13 14 15 16
4-171
CD22354A, CD22357A Functional Description
Power Supply Sequencing Do not apply input signal or load on output before powering up VCC supply. Care must be taken to ensure that DX pin goes on common back plane (with other DX pins from other chips). DX pin cannot drive >50mA before Power-Up. This will cause the part to latch up. Power-Up When power is first applied, the Power-On reset circuitry initializes the CODEC and places it in a Power-Down mode. When the CODEC returns to an active state from the PowerDown mode, the receive output is muted briefly to minimize turn-on "click". To power up the device, there are two methods available. 1. A logical zero at MCLK R /PDN will power up the device, provided FSX or FSR pulses are present. 2. Alternatively, a clock (MCLKR) must be applied to MCLKR/ PDN and FSX or FSR pulses must be present. Power-Down Two power-down modes are available. 1. A logical 1 at MCLKR/PDN, after approximately 0.5ms, will power down the device. 2. Alternatively, hold both FSX and FSR continuously low, the device will power down approximately 0.5ms after the last FSX or FSR pulse. Synchronous Operation (Transmit and Receive Sections use the Same Master Clock) The same master clock and bit-clock should be used for the receive and transmit sections. MCLKX (pin 9) is used to provide the master clock for the transmit section; the receive section will use the same master clock if the MCLKR /PDN (pin 8) is grounded (synchronous operation), or at V+ (power-down mode). MCLKR /PDN may be clocked only if a clock is provided at BCLKR /CLKSEL (pin 7) as in asynchronous operation. The BCLKX (pin 10) is used to provide the bit clock to the transmit section. In synchronous operation, this bit clock is also used for the receive section if MCLKR /PDN (pin 8) is grounded. BCLKR /CLKSEL (pin 7) is then used to select the proper internal frequency division for 1.544MHz, 1.536MHz or 2.048MHz operation (see Table below). For 1.544MHz operation, the device automatically compensates for the 193rd clock pulse each frame. Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the leading edge of BCLKX. After 8 bitclock periods, the tristate DX output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of the BCLKX. FSX and FSR must be synchronous with MCLKX.
MODE Asynchronous or Synchronous Synchronous CLOCKING OPTIONS MASTER CLOCK FREQUENCY SELECTED
BCLKR /CLKSEL (PIN 7) CD22354A () CD22357A (A) Clocked 1.536MHz or 1.544MHz 2.048MHz 1.536MHz or 1.544MHz 2.048MHz
0
1.536MHz or 1.544MHz 2.048MHz
Synchronous 1(or open circuit)
Asynchronous Operation (Transmit and Receive Sections use Separate Master Clocks) For the CD22357A, the MCLKX and MCLKR must be 2.048MHz and for the CD22354A must be 1.536MHz or 1.544MHz. These clocks need not be synchronous. However, for best transmission performance, it is recommended that MCLKX and MCLKR be synchronous. For 1.544MHz operation the device automatically compensates for the 193rd clock pulse each frame. FSX starts the encoding operation and must be synchronous with MCLKX and BCLKX. FSR starts the decoding operation and must be synchronous with BCLKR. BCLKR must be clocked in asynchronous operation. BCLKX and BCLKR may be between 64kHz - 2.04MHz. Short-Frame Sync Mode When the power is first applied, the power initialization circuitry places the CODEC in a short-frame sync mode. In this mode both frame sync pulses must be 1 bit-clock period long, with the timing relationship shown in Figure 1. With FSX high during the falling edge of the BCLKX, the next rising edge of BCLKX enables the DX tristate output buffer, which will output the sign bit. The following rising seven edges clock out the remaining seven bits upon which the next falling edge will disable the DX output. With FSR high during the falling edge of the BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven edges latch in the seven remaining bits. Long-Frame Sync Mode In this mode of operation, both of the frame sync pulses must be three or more bit-clock periods long with the timing relationship shown in Figure 2. Based on the transmit frame sync FSX, the CODEC will sense whether short or long-frame sync pulses are being used. For 64kHz operation the frame sync pulse must be kept low for a minimum of 160ns. The DX tristate output buffer is enabled with the rising edge of FSX or the rising edge of the BCLKX, whichever comes later and the first bit clocked out is the sign bit. The following seven rising edges of the BCLKX clock out the remaining seven bits. The DX output is disabled by the next falling edge of the BCLKX following the 8th rising edge or by FSX going low whichever comes later.
4-172
CD22354A, CD22357A
A rising edge on the receive frame sync, FSR, will cause the PCM data at DR to be latched in on the next falling edge of the BCLKR. The remaining seven bits are latched on the successive seven falling edges of the bit-clock (BCLKX in synchronous mode). Transmit Section The transmit section consists of a gain-adjustable input opamp, an anti-aliasing filter, a low-pass filter, a high-pass filter and a compressing A/D converter. The input op-amp drives a RC active anti-aliasing filter. This filter eliminates the need for any off-chip filtering as it provides 30dB attenuation (Min) at the sampling frequency. From this filter the signal enters a 5th order low-pass filter clocked at 128kHz, followed by a 3rd order highpass filter clock at 32kHz. The output of the high-pass filter directly drives the encoder capacitor ladder at an 8kHz sampling rate. A precision voltage reference is trimmed in manufacturing to provide an input overload of nominally 2.5VPEAK. Transmit frame sync pulse FSX controls the process. The 8-bit PCM data is clocked out at DX by the BCLKX. BCLKX can be varied from 64kHz to 2.048MHz. Receive Section The receive section consists of an expanding D/A converter and a low-pass filter which fulfills both the AT&T D3/D4 specifications and CCITT recommendations. PCM data enters the receive section at DR upon the occurrence of FSR, Receive Frame sync pulse. BCLKR, Receive Data Clock, which can range from 64kHz to 2.048MHz, clocks the 8-bit PCM data into the receive data register. A D/A conversion is performed on the 8-bit PCM data and the corresponding analog signal is held on the D/A capacitor ladder. This signal is transferred to a switched capacitor low-pass filter clocked at 128kHz to smooth the sample-and-hold signal as well as to compensate for the (SIN X)/X distortion. The filter is then followed by a second order Sallen and Key active filter capable of driving a 600 load to a level of 7.2dBm.
t XDB t WWL
TS X
t DZC
t RM
MCLK R MCLK X
t FM t PM
t WWH
1
t SBFM
2 3 4 5 6 7 8
BCLKX
t HOLD
FSX
t HF
t SF
DX 1 2
t DBD
3 4 5 6
t DZC
7 8
t HOLD
BCLKR 1
t HF
2 3 4 5 6 7 8
t SF
FSR
t HDB t SDB
t HBD
DR
1
2
3
4
5
6
7
8
FIGURE 1. SHORT FRAME-SYNC TIMING
4-173
CD22354A, CD22357A
tWWL tWWH
MCLKR MCLKX
t RM t FM
t PM
tSBFM
1
tWBH tSBFM
2 3 4
tWBL
5 6 7 8
BCLKX
tSFB
FSX t HBF
t PB t FB t RB t DZF t HBFI t DBD
2 3 4 5 6 7
t DZF
DX t HBF BCLKR 1 2 3 4 5 6 7 1
t DZC
8
t DZC
8
t HBFI
FSR
t SFB
DR
t SDB
2 3 4
t HBD
t HBD
6 7 8
1
5
FIGURE 2. LONG FRAME-SYNC TIMING
4-174

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